The present invention generally relates to processing a semiconductor substrate. In particular, the present invention relates to treating a surface of a virgin silicon oxynitride layer with an oxygen-nitrogen plasma to facilitate a reduction in line edge roughness and surface interaction with respect to subsequent 193 nm and below photoresist processing.
Achieving the objectives of miniaturization and higher packing densities continue to drive the semiconductor manufacturing industry toward improving semiconductor processing in every aspect of the fabrication process. Several factors and variables are involved in the fabrication process. For example, at least one and typically more than one photolithography process may be employed during the fabrication of a semiconductor device. Each factor and variable implemented during fabrication must be considered and improved in order to achieve the higher packing densities and smaller, more precisely formed semiconductor structures.
In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the photoresist, and an exposing source (such as optical light, X-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the photoresist mask, for a particular pattern. The lithographic coating is generally a radiation-sensitized coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive of the subject pattern. Exposure of the coating through the photoresist mask causes a chemical transformation in the exposed areas of the coating thereby making the image area either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer. The resulting pattern image in the coating, or layer, may be at least one portion of a semiconductor device that contributes to the overall structure and function of the device.
Because the photoresist is used to form features on the semiconductor devices, the integrity of the photoresist must be maintained throughout the lithography process. That is, any flaw or structural defect which is present on the photoresist may be indelibly transferred to underlying layers during a subsequent etch process wherein the photoresist is employed. However, protecting the integrity of the photoresist layer may not always prevent the formation of flawed or defective semiconductor features on the wafer. Various other layers or attributes of the wafer may be the cause of undesirable structural defects.
One example of an undesirable structural defect is line-edge roughness (LER), as seen on a wafer 10 in Prior Art FIG. 1. LER refers to surface variations and irregularities particularly on the sidewalls of a feature, but also on the top and bottom perimeters of the feature. LER may originate with the photoresist layer which can be caused by various factors such as LER on chrome patterns residing on the reticle, image contrast in a system for generating the photoresist pattern, a plasma etch process which can be used to pattern the photoresist, natural properties of the photoresist materials, and the photoresist processing method.
In addition, LER on a semiconductor feature can result from the radiation used to process a photoresist formed over an underlying layer. For example, thinner photoresist layers are typically utilized when forming smaller features having higher resolution. Thus, shorter wavelength radiation from 193 nm and lower is employed to process these photoresists. However, photoresists processed with the shorter wavelength radiation experience damaging surface interactions with the underlying layer. That is, when irradiated with 193 nm and lower radiation, the surface of the photoresist interacts with the surface of the underlying layer causing LER to occur on the developed photoresist.
As the fabrication trend of semiconductors relies heavily on producing more miniaturized and more densely packed wafers, the use of photoresists using 193 nm and below radiation is substantially increasing in order to meet the demands of the industry. Undesirable surface interactions between the photoresist and the underlying layer appear to be more serious for 193 nm photoresists, which have less etch resistance than resists used at higher wavelengths such as 248 nm, 365 nm, etc. Because the photoresist material is relatively soft and thin when irradiated at this desired wavelength, the radiation used to pattern the photoresist may undesirably affect the underlying layer. The condition may even worsen for wavelengths below 193 nm, such as 157 nm photoresists. Moreover, LER can interfere with accurate metrology and adversely affect device performance.
With respect to FIG. 1, for example, forming 300 nm pitch trenches 20 in a photoresist layer 30 overlying a silicon oxynitride 40 and a substrate 50 using 193 nm photoresist processing results in substantial LER 60 on the surfaces of the trenches. In addition, signs of undesirable surface interaction may be observed on the top surface 70 of the layer. Conventional resolutions to these problems involve forming an undoped oxide cap after the layer is formed but before photoresist deposition and processing begins. However, the occurrences of the surface abnormalities and poor feature profiles persist despite the oxide cap.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides a novel system and method for mitigating the occurrence of surface abnormalities on etched semiconductor features caused by undesirable surface interaction between a surface of a layer and the photoresist formed thereon during a lithography process. More specifically, the present invention provides a system and method for reducing line edge roughness (LER) as it may occur on the surface of about 193 nm or lower photoresists overlying a silicon oxynitride or silicon nitride layer. This aspect of the present invention is accomplished in part by applying a plasma treatment onto the surface of the layer before a photoresist is formed thereon. In addition, the present invention is accomplished in part by employing a monitoring device to oversee the plasma treatment and to determine whether the plasma treatment has been effective.
For example, a virgin silicon oxynitride layer may undergo a plasma treatment before a photoresist is formed thereon and patterned. The layer may be exposed to a first plasma containing oxygen and nitrogen followed by an optional second plasma containing nitrogen and hydrogen. The surface of the silicon oxynitride layer is treated with the first plasma in order protect it from undesirable effects caused by short wavelength photoresist processing. Examples of undesirable effects include surface interaction between the surface of the silicon oxynitride layer and the photoresist layer, resulting in LER on the developed photoresist layer. The LER on the developed photoresist layer may be transferred to the underlying silicon oxynitride layer, thereby interfering with device formation and performance.
The first plasma treatment containing oxygen and nitrogen is not employed under conventional etch process conditions. Therefore, the plasma treatment does not substantially etch, remove, or damage in any way any portion of the exposed silicon oxynitride layer or any other layer that may be exposed to the treatment. The first plasma treatment modifies the surface of the silicon oxynitride layer in such a manner to prevent unwanted surface interaction arising from subsequent short wavelength photoresist processing. After the short wavelength photoresist is patterned, conventional etchants employed under etch process conditions may be utilized to selectively remove exposed portions of the silicon oxynitride layer as desired. Furthermore, a monitor processor may be employed during the fabrication process to determine whether the plasma treatment has been administered, to adjust plasma treatment components as needed and to provide feedback information to a fabrication process and/or system as it relates to the status of the modified layer.
One aspect of the present invention relates to a method for mitigating surface abnormalities on a semiconductor structure. The method involves providing a semiconductor substrate having a layer formed thereon; exposing the layer to a plasma treatment in order to mitigate surface interactions between the layer and a subsequently formed photoresist without substantially etching the layer, the plasma containing oxygen and nitrogen; forming a patterned photoresist layer over the treated layer; and etching the treated layer through one or more openings in the patterned photoresist layer.
Another aspect of the present invention relates to a method for mitigating surface abnormalities in situ on a semiconductor structure. The method involves providing a semiconductor substrate having a virgin silicon oxynitride layer deposited thereon; exposing the silicon oxynitride layer to a plasma treatment in order to mitigate surface interactions between the silicon oxynitride layer and a subsequently formed photoresist without substantially etching the silicon oxynitride layer, the plasma containing oxygen and nitrogen; determining whether the silicon oxynitride layer has been treated by employing a monitor processor; forming a patterned photoresist layer over the treated silicon oxynitride layer; and etching the treated silicon oxynitride layer through openings of the patterned photoresist layer to form a semiconductor feature.
Yet another aspect of the present invention relates to a system for mitigating LER in situ during fabrication of a semiconductor structure. The system includes a layer containing silicon oxynitride, the layer being contained within a chamber and being exposed to a plasma treatment, which is selective to the layer and which does not act as an etchant; a plasma chamber for treating the layer with the plasma treatment; one or more plasma treatment components operatively coupled to the plasma treatment for administering the plasma treatment; and a monitor processor operatively connected to the chamber and the wafer for controlling the plasma treatment and for determining whether the layer has been protected against surface abnormalities.